Method for controlling Timing of Memory Device

The timing control of the memory device that can adjust the internal timing margin depending on the number of cycles the column method is provided. A memory device which requires high speed operation, as the column number of cycles increases is reduced timing margins needed to perform operations according to the access of a new word line. Reduced timing margin is a factor of lowering the operating characteristics of the memory device at the time of high-speed operation. To this end, the column corresponding to the number of cycles to set the time at which the word line is disabled. In addition, bit lines are equalized by adjusting the amount of time that should ensure the timing margin needed for activation of a new word line. Column the delay path until the set differently along the delay path to the internal command to the column number of cycles, and the bit line equalizing signal for adjustment of the equalizing start time occurs for the time on which the disabling of a word line start the setting depends on the number of cycles. In addition, the counting time of the activated word line to control the time at which the word line is disabled according to the column number of cycles.