Activity-driven optimised bus-specific-clock-gating for ultra-low-power smart space applications

Power consumption is the most important issue in circuit design nowadays, and clock gating is the most widely used technique to reduce the dynamic power at register transfer level. The traditional clock gating style using an XOR gate to generate a gated clock was proposed but has not been well studied. It can be extended to multiple flip-flops easily but the power performance is not optimal. In this study, the authors propose a fine-grained activity-driven optimised bus-specific-clock-gating for ultra-low-power smart spaces applications, which can selectively choose qualified flip-flops to be gated based on their output switching activities to optimise the power. This technique has been experimented on ISCAS’89 benchmark circuits, and average power can be reduced by 19.21%.

[1]  Luca Benini,et al.  Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers , 1999, TODE.

[2]  Farid N. Najm,et al.  A survey of power estimation techniques in VLSI circuits , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[3]  Kurt Keutzer,et al.  Estimation of average switching activity in combinational and sequential circuits , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[4]  Sujit Dey,et al.  High-Level Power Analysis and Optimization , 1997 .

[5]  Gaetano Palumbo,et al.  Evaluation on power reduction applying gated clock approaches , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[6]  Luca Benini,et al.  A scalable algorithm for RTL insertion of gated clocks based on ODCs computation , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  Jagdish C. Rao,et al.  Clock gating for power optimization in ASIC design cycle theory & practice , 2008, Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08).

[8]  Gila Kamhi,et al.  A new paradigm for synthesis and propagation of clock gating conditions , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[9]  Takashi Kambe,et al.  A method of redundant clocking detection and power reduction at RT level design , 1997, Proceedings of 1997 International Symposium on Low Power Electronics and Design.

[10]  Tomás Lang,et al.  Individual flip-flops with gated clocks for low power datapaths , 1997 .

[11]  Marios C. Papaefthymiou,et al.  Precomputation-based sequential logic optimization for low power , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[12]  Paul D. Franzon,et al.  FreePDK: An Open-Source Variation-Aware Design Kit , 2007, 2007 IEEE International Conference on Microelectronic Systems Education (MSE'07).