Optimization of the VT-control method for low-power ultra-thin double-gate SOI logic circuits

Application of the VT-control method is studied in ultrathin double-gate (DG) SOI inverter, as the simplest building block of SOI logic circuits. Two control voltages, VCN and VCP, are applied to the back-gates of the n-type and p-type transistors, respectively, to reduce the leakage current when the inverter is in the idle mode. Simulations with DESSIS disclose that both control voltages may be set at an optimum value for a given circuit activity, leading to the lowest possible gate power-delay product. Simulations have been performed for 10 nm gate-length technology at the end of the ITRS roadmap. These results indicate that the optimized VT-control method is a promising way for realizing low-power SOI logic circuits.

[1]  T. Kaga,et al.  Variable threshold-voltage SOI CMOSFETs with implanted back-gate electrodes for power-managed low-power and high-speed sub-1-V ULSIs , 1996, 1996 Symposium on VLSI Technology. Digest of Technical Papers.

[2]  Vivek De,et al.  Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[3]  Vivek De,et al.  Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs , 2001, ISLPED '01.

[4]  Kaushik Roy,et al.  Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[5]  Young,et al.  Dual Threshold Voltages And Substrate Bias: Keys To High Performance, Low Power, 0.1 /spl mu/m Logic Designs , 1997, 1997 Symposium on VLSI Technology.

[6]  Davood Shahrjerdi,et al.  Power optimization in ultra-thin DG SOI logic circuits by means of VT-control method , 2004 .

[7]  D. A. Antoniadis,et al.  Effect of back-gate biasing on the performance and leakage control in deeply scaled SOI MOSFETs , 2002, 2002 IEEE International SOI Conference.

[8]  Davood Shahrjerdi,et al.  Optimization of the VT control method for low-power ultra-thin double-gate SOI logic circuits , 2005, Integr..

[9]  Dimitri A. Antoniadis,et al.  Back-gated CMOS on SOIAS for dynamic threshold voltage control , 1997 .