Bit-splitting for testability enhancement in scan-based design

A new design for testability technique, the bit-splitting for testability enhancement in scan-based design, is presented. The idea is to split some inputs into two independent variables to make the original circuit more controllable and thus more testable. Theoretical study and experiments with two-level circuits indicate that this method can easily provide 100% Single-Path-Sensitization Path Delay Fault Testability (SPDFT). Fault coverage can also be improved for the multi-level circuits and when constrained transformations are used, multi-level circuit can also be made 100% SPDFT.<<ETX>>

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