An AND-type match-line scheme for energy-efficient content addressable memories

An AND-type match-line scheme is fabricated in a 0.18 /spl mu/m 1.8V CMOS process. The 256/spl times/128b CAM achieves a faster search time and a 20% energy reduction compared with NOR designs. This AND-type circuit has a search time of 1.75ns with an energy of 0.57fJ/bit/search.

[1]  Oscal T.-C. Chen,et al.  A power-efficient wide-range phase-locked loop , 2002, IEEE J. Solid State Circuits.

[2]  Hoi-Jun Yoo,et al.  A 0.7fJ/bit/search, 2.2ns search time hybrid type TCAM architecture , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[3]  Jinn-Shyan Wang,et al.  Analysis and design of high-speed and low-power CMOS PLAs , 2001 .

[4]  K. Pagiamtzis,et al.  A low-power content-addressable memory (CAM) using pipelined hierarchical search scheme , 2004, IEEE Journal of Solid-State Circuits.

[5]  Hoi-Jun Yoo,et al.  A 0.7-fJ/bit/search 2.2-ns search time hybrid-type TCAM architecture , 2004, IEEE Journal of Solid-State Circuits.

[6]  K. J. Schultz,et al.  Fully Parallel 30-MHz , 2 . 5-Mb CAM , 1998 .

[7]  Christer Svensson,et al.  New domino logic precharged by clock and data , 1993 .