A Novel Low Power Energy Efficient SRAM Cell With Reduced Power Consumption using MTCMOS Technique

In modern high performance integrated circuits, maximum of the total active mode energy is consumed due to leakage current. SRAM cell array is main source of leakage current since majority of transistor are utilized for on-chip memory in today high performance microprocessor and system on chip designs. Therefore the design of low leakage SRAM is required. Reducing power dissipation, supply voltage, leakage currents, area of chip are the most important parameters in today`s VLSI designs. But scaling of these parameters will lead to drastic increase in sub threshold leakage currents and power dissipation because of that performance of the design is degraded. So to overcome these issues it is better to concentrate on reduction of active leakage currents and dynamic power dissipation by using power reduction techniques. In this paper 9T SRAM (data retention p-gated) cell for low voltage and energy constrain application is analyzed with respect to power dissipation, area and delay. The analyzed design of 9T SRAM cell with MTCMOS technique has been proposed. Designed circuits are simulated in Microwind 3.1 VLSI CAD Tool in 90 and 65nm CMOS technology.