I/sub DDQ/ testing of oscillating bridging faults in CMOS combinational circuits

IDDQ testing has been shown to be an efficient way to test CMOS technology circuits when realistic failures, bridges among others, are considered. A particular group of bridging faults cause the circuit to oscillate because of unstable feedback. This paper focuses on the evaluation of IDDQ testability for these bridging faults. An electrical circuit model allows the analytic derivation of characteristics of the oscillating IDD behaviour. It is shown that oscillating faults are testable by classical IDDQ sensors. The knowledge of the ripple frequency and the maximum and minimum values of the oscillating IDD current allows the characterisation of the IDDQ levels, and it is useful in the design or choice of a current sensor in the general case