A novel PLL based on phase comparison between two signals with different frequencies
暂无分享,去创建一个
[1] Kyoohyun Lim,et al. A low-noise phase-locked loop design by loop bandwidth optimization , 2000, IEEE Journal of Solid-State Circuits.
[2] Wei Zhou,et al. A precision frequency standard comparison method and instrument , 2000, Proceedings of the 2000 IEEE/EIA International Frequency Control Symposium and Exhibition (Cat. No.00CH37052).
[3] H. Joba,et al. Overview of the evolution of PLL synthesizers used in mobile terminals , 2004, Proceedings. 2004 IEEE Radio and Wireless Conference (IEEE Cat. No.04TH8746).
[4] Wei Zhou,et al. A high-resolution frequency standard comparator based on a special phase comparison approach , 2004, Proceedings of the 2004 IEEE International Frequency Control Symposium and Exposition, 2004..
[5] Wei Zhou. Systematic Research on High‐Accuracy Frequency Measurements and Control , 2001 .
[6] S. Nati,et al. A monolithic gallium arsenide interval timer IC with integrated PLL clock synthesis having 500-ps single shot resolution , 1997 .
[7] Wancheng Zhang,et al. A Novel Hybrid Phase-Locked-Loop Frequency Synthesizer Using Single-Electron Devices and CMOS Transistors , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.
[8] Payam Heydari. Analysis of the PLL jitter due to power/ground and substrate noise , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.