Development of Carbon Nanotube Based Through-Silicon Vias

The design and development of reliable 3D integrated systems require high performance interconnects, which in turn are largely dependent on the choice of filler materials used in through-silicon vias (TSVs). Copper, tungsten, and poly-silicon have been explored as filler materials; however, issues such as thermal incompatibility, electromigration, and high resistivity are still a bottleneck. In this paper, we investigate single-walled carbon nanotube (CNT) bundles as a prospective filler material for TSVs and have provided an analysis of CNT based TSVs for package and chip interconnects. The interconnects are fundamental bottlenecks to achieving high performance and reliability. We have provided electrical modeling and performed simulations on TSVs with copper and carbon nanotubes. The results from the CNT based TSVs were greatly superior to those from the conventional vias with copper.

[1]  Wolfgang Hoenlein,et al.  Growth of isolated carbon nanotubes with lithographically defined diameter and location , 2003 .

[2]  John H. Lau,et al.  Development of through silicon via (TSV) interposer technology for large die (21×21mm) fine-pitch Cu/low-k FCBGA package , 2009, 2009 59th Electronic Components and Technology Conference.

[3]  P. Burke.  Luttinger liquid theory as a model of the gigahertz electrical properties of carbon nanotubes , 2002 .

[4]  A. Kawabata,et al.  Low-resistance multi-walled carbon nanotube vias with parallel channel conduction of inner shells [IC interconnect applications] , 2005, Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005..

[5]  Jun Li,et al.  Carbon Nanotube Based Interconnect Technology: Opportunities and Challenges , 2007 .

[6]  S. Yoon,et al.  High RF performance TSV silicon carrier for high frequency application , 2008, 2008 58th Electronic Components and Technology Conference.

[7]  J. Meindl,et al.  Performance comparison between carbon nanotube and copper interconnects for GSI , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[8]  P. Leduc,et al.  High frequency characterization and modeling of high density TSV in 3D integrated circuits , 2009, 2009 IEEE Workshop on Signal Propagation on Interconnects.

[9]  Eby G. Friedman,et al.  Three-dimensional Integrated Circuit Design , 2008 .

[10]  S. Datta.  Electronic transport in mesoscopic systems , 1995 .

[11]  J. Meindl,et al.  Performance comparison between carbon nanotube and copper interconnects for gigascale integration (GSI) , 2005, IEEE Electron Device Letters.

[12]  M. Meyyappan,et al.  Bottom-up approach for carbon nanotube interconnects , 2003 .

[13]  W. Steinhögl,et al.  Comprehensive study of the resistivity of copper wires with lateral dimensions of 100 nm and smaller , 2005 .

[14]  S. Wind,et al.  Carbon nanotube electronics , 2003, Digest. International Electron Devices Meeting,.

[15]  Mitsumasa Koyanagi,et al.  Tungsten Through-Silicon Via Technology for Three-Dimensional LSIs , 2008 .

[16]  Joungho Kim,et al.  High Frequency Electrical Model of Through Wafer Via for 3-D Stacked Chip Packaging , 2006, 2006 1st Electronic Systemintegration Technology Conference.

[17]  P. Burke,et al.  Microwave transport in metallic single-walled carbon nanotubes. , 2005, Nano letters.

[18]  G. Duesberg,et al.  Carbon nanotubes for interconnect applications , 2002, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[19]  Kaustav Banerjee,et al.  Are carbon nanotubes the future of VLSI interconnections? , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[20]  S. Datta.  Electrical resistance: an atomistic view , 2004, cond-mat/0408319.

[21]  P. Ajayan,et al.  Reliability and current carrying capacity of carbon nanotubes , 2001 .

[22]  S. Nai,et al.  Suppressing intermetallic compound growth in SnAgCu solder joints with addition of carbon nanotubes , 2008, 2008 2nd IEEE International Nanoelectronics Conference.