Hierarchical automatic behavioral model generation of nonlinear analog circuits based on nonlinear symbolic techniques

We present an extended method of automatic behavioral model generation for nonlinear analog circuits. The focus is on a decrease of simulation time. A procedural model formulation approach is introduced, together with a new simplification method based on the recognition of physical transistor properties of the element models. The simplification process is performed with respect to simulation time, and a hierarchical modeling approach is proposed. The result of these extensions are models with an obvious speed-up in simulation time compared to the simulation of the original netlists.

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