论文信息 - A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology - 字舞流文

A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology

William J. Dally | Yanqing Zhang | Brucek Khailany | Stephen G. Tell | Jason Clemons | Stephen W. Keckler | Joel S. Emer | Brian Zimmer | C. Thomas Gray | Nan Jiang | C. T. Gray | Matthew Fojtik | Rangharajan Venkatesan | Alicia Klinefelter | Yakun Sophia Shao | Ben Keller | Nathaniel Pinckney | Priyanka Raina | W. Dally | Rangharajan Venkatesan | J. Emer | S. Keckler | Jason Clemons | B. Zimmer | Ben Keller | Matthew R. Fojtik | N. Pinckney | S. Tell | Y. Shao | Priyanka Raina | Alicia Klinefelter | Nan Jiang | Yanqing Zhang | Brucek Khailany