论文信息 - High performance DES encryption in Virtex/sup TM/ FPGAs using JBits/sup TM/

High performance DES encryption in Virtex/sup TM/ FPGAs using JBits/sup TM/

A JBits implementation of the Data Encryption Standard (DES) algorithm in a Virtex FPGA is described. The Virtex architecture efficiently implements the DES primitive operations, and permits a high degree of pipelining. JBits provides a Java-based Application Programming Interface (API) for the run-time creation and modification of the configuration bitstream. This allows dynamic circuit specialization based on a specific key and mode (encrypt or decrypt). The key schedule is computed entirely in software, and is part of the bitstream. As a result, all cryptographic key input and subkey generation logic are removed from the fully unrolled datapath. When combined with a speed efficient layout the result is a throughput of over 10 Gigabits per second. This exceeds the performance of a recently announced DES ASIC.

Cameron Patterson

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