论文信息 - Analysis of multifin n-FinFET for analog performance at 30nm gate length

Analysis of multifin n-FinFET for analog performance at 30nm gate length

Multi-gate FET, a self-aligned structure (FinFET) is one of the most promising device to address leakage issues and short channel effects in deeply scaled CMOS technology nodes. In order to improve the analog performance of the system the figure of merits (FoMs) of device technology should relate to those of circuit level FoMs. In this paper, based on Visual-TCAD 3-D numerical simulations, we analyze the effect of multi-fin structure and resulting impact of various RF parameters like transconductance, output resistance, intrinsic gain, parasitic resistance and capacitance, mobility, early voltage, drain conductance and cut-off frequency which affects the analog behavior of multi-fin FinFETs device.

S. S. Rathod | Reena S. Sonkusare

[1] Behzad Razavi. CMOS technology characterization for analog and RF design , 1999 .

[2] Niraj K. Jha,et al. FinPrin: FinFET Logic Circuit Analysis and Optimization Under PVT Variations , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3] N. Collaert,et al. Analysis of the parasitic S/D resistance in multiple-gate FETs , 2005, IEEE Transactions on Electron Devices.

[4] Mansun Chan,et al. Analysis of Geometry-Dependent Parasitics in Multifin Double-Gate FinFETs , 2007, IEEE Transactions on Electron Devices.

[5] Jason C. S. Woo,et al. Channel engineering for analog device design in deep submicron CMOS technology for system on chip applications , 2002 .

[6] O. Faynot,et al. Multiple gate devices: advantages and challenges , 2005 .

[8] Jean-Pierre Colinge,et al. Multiple-gate SOI MOSFETs , 2004 .

[9] G. Knoblinger,et al. Analog circuits using FinFETs: benefits in speed-accuracy-power trade-off and simulation of parasitic effects , 2007 .

[10] Ali M. Niknejad,et al. BSIM—SPICE Models Enable FinFET and UTB IC Designs , 2013, IEEE Access.

[11] Vaidyanathan Subramanian,et al. Multiple Gate Field-Effect Transistors for Future CMOS Technologies , 2010 .

[12] Variability Origins of Parasitic Resistance in FinFETs With Silicided Source/Drain , 2012, IEEE Electron Device Letters.

[13] G. Pei,et al. FinFET design considerations based on 3-D simulation and analytical modeling , 2002 .