$$\hbox {TM}^{2}$$TM2C: a software transactional memory for many-cores

Transactional memory is an appealing paradigm for concurrent systems. Many software implementations of the paradigm were proposed in the past two decades for both shared memory multi-core systems and clusters of distributed machines. Chip manufacturers have however started producing many-core architectures, with low network-on-chip communication latencies and limited support for cache coherence, rendering existing transactional-memory implementations inapplicable. This paper presents $$\hbox {TM}^{2}\hbox {C}$$TM2C, the first software transactional memory protocol for many-core systems, hence featuring transactions that are both distributed and leverage shared memory. $$\hbox {TM}^{2}\hbox {C}$$TM2C exploits fast messages over network-on-chip to make accesses to shared data coherent. In particular, it allows visible read accesses to detect conflicts eagerly and incorporates the first distributed contention manager that guarantees the commit of all transactions. We evaluate $$\hbox {TM}^{2}\hbox {C}$$TM2C on Intel, AMD and Tilera architectures, ranging from common multi-cores to experimental many-cores. We build upon new message-passing protocols, based on both software and hardware, which are interesting in their own right. Our results on various benchmarks, including realistic banking and MapReduce applications, show that $$\hbox {TM}^{2}\hbox {C}$$TM2C scales well regardless of the underlying platform.