A 10-b, 100-MS/s CMOS A/D converter

A new architecture for a CMOS A/D converter overcomes many of the known problems in the parallel operation of multiple pipelined stages. The input signal is sampled in one channel, and after quantization to 4 b, the residue is distributed into many channels. A prototype implemented in 1-/spl mu/m CMOS achieves 60 dB signal-to-noise plus distortion ratio (SNDR) at low conversion rates, with a resolution bandwidth of greater than 20 MHz. The SNDR drops by 3 dB at a 95 MHz conversion rate, and the bandwidth remains the same.

[1]  Y.-C. Jenq,et al.  Digital spectra of nonuniformly sampled signals: fundamentals and high-speed waveform digitizers , 1988 .

[2]  Masaki Ishida,et al.  A 10-b 100-Msample/s pipelined subranging BiCMOS ADC , 1993 .

[3]  W. Black,et al.  Time interleaved converter arrays , 1980, 1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[4]  Germano Nicollini,et al.  A fully differential sample-and-hold circuit for high-speed applications , 1989 .

[5]  M.J.M. Pelgrom,et al.  Matching properties of MOS transistors , 1989 .

[6]  A. A. Abidi,et al.  A CMOS interface IC for CCD imagers , 1993, 1993 International Symposium on VLSI Technology, Systems, and Applications Proceedings of Technical Papers.

[7]  M.J.M. Pelgrom.  A 10-b 50-MHz CMOS D/A converter with 75- Omega buffer , 1990 .

[8]  Paul R. Gray,et al.  Design considerations for low-power, high-speed CMOS analog/digital converters , 1994, Proceedings of 1994 IEEE Symposium on Low Power Electronics.

[9]  Paul R. Gray,et al.  An 8-b 85-MS/s parallel pipeline A/D converter in 1- mu m CMOS , 1993 .

[10]  G. Geelen,et al.  A fast-settling CMOS op amp for SC circuits with 90-dB DC gain , 1990 .

[11]  Bram Nauta,et al.  A 70 MSample/s 110 mW 8 b CMOS folding interpolating A/D Converter , 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

[12]  K. Hirata,et al.  A 10 b 50 MHz pipelined CMOS A/D converter with S/H , 1993 .

[13]  A.G.W. Venes,et al.  An 80 MHz 80 mW 8 b CMOS folding A/D converter with distributed T/H preprocessing , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[14]  Paul R. Gray,et al.  A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3- mu m CMOS , 1991 .

[15]  R. Petschacher,et al.  A 10-b 75-MSPS subranging A/D converter with integrated sample and hold , 1990 .

[16]  Toshio Kumamoto,et al.  A 10-b 50 MS/s 500-mW A/D converter using a differential-voltage subconverter , 1994 .

[17]  L. R. Carley,et al.  An 85 mW, 10 b, 40 Msample/s CMOS parallel-pipelined ADC , 1995 .

[18]  P. Vorenkamp,et al.  A 10 b 50 MS/s pipelined ADC , 1992, 1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[19]  S. H. Lewis,et al.  A pipelined 5-Msample/s 9-bit analog-to-digital converter , 1987 .

[20]  Christopher W. Mangelsdorf.  A 400-MHz input flash converter with error correction , 1990 .

[21]  T. Hornak,et al.  A 1-GHz 6-bit ADC system , 1987 .

[22]  Asad A. Abidi,et al.  A 10-b, 75-MHz two-stage pipelined bipolar A/D converter , 1993 .