Code restructuring for improving execution efficiency, code size and power consumption for embedded

Many embedded systems such as personal digital assistants (PDAs), cellular phones, etc. involve heavy use of digital signal processing and are thus based on Digital Signal Processors (DSPs). DSPs such as the TMS320C2x and the DSP5600x have irregular data-paths that typically the result of application speciic needs (such as chaining multiply-accumulate operations, etc). EEcient code generation for such embedded DSP processors is a challenging problem because of the additional constraints such as tight memory and low power consumption demands, resulting in the need for compact code. In this work, we address the problem of generating compact and eecient code for embedded DSP processors. Most of the DSP instruction set architectures (ISAs) feature intra instruction parallelism (IIP) enabling individual operations to be executed in parallel with a complex instruction. A reduction in generated code size and improved performance can be achieved by exploiting this parallelism present in such ISAs. In this work, we present a code restructuring technique to fully exploit this parallelism through maximal utilization of the complex instructions present in the DSP instruction set. We formulate this problem as a maximal beneet code restructuring problem, which is to derive the arrangement of statements in a basic block to maximally exploit IIP without violating data dependencies. This problem is equivalent to Precedence Constrained Hamilto-nian Path Problem for DAGs and the Traveling Salesman Problem (PTSP) in general, both of which are NP-hard. A heuristic is then presented to solve the problem. We have implemented this heuristic in the SPAM compiler targeted to generate code for the TMS320C25 DSP. We tested our framework on a number of benchmarks and found that the performance of the generated code|measured in dynamic instruction cycle counts|improves by as much as 7% with an average of 3%. The average code size reduction over code compiled without exploiting parallelism is 2.9%. We also studied the eeect of loop unrolling on the available IIP within a basic block. The improvement in static code size can be traded oo with a reduction in the number of dynamic instruction cycle counts through loop unrolling techniques. Finally we measure power eeciency of the generated code and show that not only is code size reduced but also power consumption is signiicantly reduced. 1 Introduction Embedded processors are widely used in a variety of applications such as cellular phones, pagers, printers, copiers, digital cameras, automobiles, ight navigation systems etc. Unlike general purpose processors, embedded …