Terascale integration via a redesign of the crossbar based on a vertical arrangement of poly-Si nanowires

The race of integrated-circuit technology towards high bit density has already brought transistor densities of the order of 109 cm−2, while keeping conventional circuit layouts. Crossbar structures are widely believed to meet the requirements of high bit density along with sustainable interconnection complexity avoiding the dramatic cost increase of the manufacturing facilities required by advanced lithography. In this work we demonstrate the possibility of producing poly-Si nanowires preserving bulk electrical properties that are nonetheless so dense as to allow cross-point density in excess of 1011 cm−2. This result could be achieved by organizing silicon nanowires in nearly vertical arrays.

[1]  U. Gösele,et al.  Growth, thermodynamics, and electrical properties of silicon nanowires. , 2010, Chemical reviews.

[2]  L. Canham,et al.  Gaining light from silicon , 2000, Nature.

[3]  Gianfranco Cerofolini,et al.  Molecular electronics in silico , 2008 .

[4]  Michael E Phelps,et al.  Systems Biology and New Technologies Enable Predictive and Preventative Medicine , 2004, Science.

[5]  Mark A. Reed,et al.  Label-free immunodetection with CMOS-compatible semiconducting nanowires , 2007, Nature.

[6]  Yiping Zhao,et al.  Multi-silicon ridge nanofabrication by repeated edge lithography , 2009, Nanotechnology.

[7]  R. Waser.  Resistive non-volatile memory devices (Invited Paper) , 2009 .

[8]  Jeffrey Bokor,et al.  Sublithographic nanofabrication technology for nanocatalysts and DNA chips , 2003 .

[9]  C. Galati,et al.  The addition of functional groups to silicon via hydrosilation of 1-alkynes at hydrogen-terminated, 1 × 1 reconstructed, (100) silicon surfaces , 2003 .

[10]  L. Renna,et al.  A hybrid approach to nanoelectronics , 2005 .

[11]  Three-dimensional interconnect technology for ultra-compact MMICs , 1997 .

[12]  Marco Camalleri,et al.  Strategies for nanoelectronics , 2005 .

[13]  D. C. Flanders,et al.  Generation of <50 nm period gratings using edge defined techniques , 1983 .

[14]  G. Cerofolini,et al.  A hybrid micro-nano-molecular route for nonvolatile memories , 2006 .

[15]  James R Heath,et al.  Superlattice nanowire pattern transfer (SNAP). , 2008, Accounts of chemical research.

[16]  Gengfeng Zheng,et al.  Nanowire sensors for medicine and the life sciences. , 2006, Nanomedicine.

[17]  G. Ferla,et al.  Toward a Hybrid Micro-nanoelectronics , 2002 .

[18]  Michael C. McAlpine,et al.  Development of ultra-high density silicon nanowire arrays for electronics applications , 2008 .

[19]  N. Melosh,et al.  Ultrahigh-Density Nanowire Lattices and Circuits , 2003, Science.

[20]  Gregory S. Snider,et al.  A Defect-Tolerant Computer Architecture: Opportunities for Nanotechnology , 1998 .

[21]  Valeria Casuscelli,et al.  Steps farther towards micro-nano-mole integration via the multispacer patterning technique , 2007 .

[22]  L. Canham.  Silicon quantum wire array fabrication by electrochemical and chemical dissolution of wafers , 1990 .

[23]  Bonnie A. Sheriff,et al.  A 160-kilobit molecular electronic memory patterned at 1011 bits per square centimetre , 2007, Nature.

[24]  Jeffrey Bokor,et al.  Fabrication of Sub-10-nm Silicon Nanowire Arrays by Size Reduction Lithography , 2003 .

[25]  J. F. Stoddart,et al.  Nanoscale molecular-switch crossbar circuits , 2003 .

[26]  Paolo Amato,et al.  The multi-spacer patterning technique: a non-lithographic technique for terascale integration , 2008 .