Analysis and Measurement of Spurious Emission and Phase Noise Performance of an RF All-Digital Phase Locked Loop using a Frequency Discriminator

A frequency discriminator in all-digital phase locked loops (ADPLLs) for RF-synthesis has to fulfill several tough requirements. The most important requirements are the in-band phase noise performance and knowledge about offset frequencies of the spurious emissions, because the ADPLL should fulfill several wireless communication standard requirements like UMTS and GSM. This paper presents a theoretical derivation, simulative analysis, and measurement results for the in-band phase noise level and the offset frequencies of spurious emissions of an ADPLL with a two-bit Frequency Discriminator implemented in a standard 0.13 mum CMOS technology

[1]  Poras T. Balsara,et al.  1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[2]  L. Maurer,et al.  Analysis of a Two-Bit Frequency Discriminator in an All Digital Phase Locked Loop for RF-Modulation and RF-Frequency Synthesis , 2006, 2006 European Conference on Wireless Technology.

[3]  Ian Galton.  Higher-order delta-sigma frequency-to-digital conversion , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

[4]  M. Høvin,et al.  Delta-sigma modulators using frequency-modulated intermediate values , 1997, IEEE J. Solid State Circuits.