Implementation of High Speed FIR Filter using Serial and Parallel Distributed Arithmetic Algorithm
暂无分享,去创建一个
[1] B. S. Sohi,et al. Efficient design of application specific DSP cores using FPGAs , 2001, ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549).
[2] David V. Anderson,et al. Hardware-efficient distributed arithmetic architecture for high-order digital filters , 2005, Proceedings. (ICASSP '05). IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005..
[3] Louis G. Johnson,et al. Reducing hardware requirement in FIR filter design , 2000, 2000 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.00CH37100).
[4] Masuri Othman,et al. An Algorithm Proposed for FIR Filter Coefficients Representation , 2007 .
[5] Samir Palnitkar,et al. Verilog HDL: a guide to digital design and synthesis , 1996 .
[6] Mitsuru Yamada,et al. A high-speed FIR digital filter with CSD coefficients implemented on FPGA , 2001, ASP-DAC '01.
[7] Stephen A. Dyer,et al. Digital signal processing , 2018, 8th International Multitopic Conference, 2004. Proceedings of INMIC 2004..
[8] M. Martinez-Peiro,et al. A comparison between lattice, cascade and direct form FIR filter structures by using a FPGA bit-serial distributed arithmetic implementation , 1999, ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357).
[9] S.A. White,et al. Applications of distributed arithmetic to digital signal processing: a tutorial review , 1989, IEEE ASSP Magazine.