Simulation of physical faults in VLSI circuits

Describes an approach for performing transistor-level logical fault simulation of VLSI MOS circuits. The method is based on a recently introduced algebraic approach to switch-level simulation. The faults considered are grouped into four sets: node stuck-at, transistor stuck-open, transistor stuck-on, and bridging faults. The authors consider concurrent fault simulation implementation, and compare, using typical examples, the computational and storage requirements of including all faults in the fault list in one simulation run versus using multiple runs with different fault groupings. Both output voltage and supply current monitoring are used for fault detection.<<ETX>>