Experiments using automatic physical design techniques for optimizing circuit performance

A system that accepts a transistor level net list, tunes it for high performance, and automatically lays it out is described. The system consists primarily of two components, TILOS and SC2D. The first component, TILOS, adjusts transistor sizes and reorders series devices to meet user-supplied performance specifications, while using the smallest size transistors possible. The sized net list is placed and routed by SC2D, which produces a virtual-grid layout ready for compaction. The algorithms and procedures are described, and their effect is illustrated with several examples, ranging from a few dozens of transistors to tens of thousands.<<ETX>>

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