Implementing 2 D Memory Buffers for MPEG

In MPEG applications, many of the algorithms are data intensive and require high levels of data locality and data reusability. A crucial performance bottleneck is the enormous data bandwidth the involved algorithms require. We focus on improving the speed of hardware MPEG decoders by using a 2-dimensional storage structure as part of a dedicated memory organization. The 2D storage makes the accesses to rectangular blocks of data more efficient. This is achieved by reduced number of memory accesses and improved data bandwidth utilization. The paper presents a generic structural design of the 2D storage, realized in VHDL. Feasible dimensions of the storage structure and the corresponding speed-ups get particular emphasis in the presented research effort. Results are obtained after the VHDL code is synthesized for the recent platform FPGA technology of Xilinx – Virtex II Pro. Reported data are related to the feasible sizes of the 2D buffer in terms of reconfigurable hardware resources consumed. Experimental data are compared for a 24x24 bytes 2D data storage and block patterns of 8x8 bytes versus linear memory with data bandwidth of 8, 16 and 32 bits. At reasonable hardware costs, the speed-up, estimated by simulations, may reach in some of the experimental cases up to a factor of 39. Structured tabular data are presented and can be utilized for taking design decisions with respect to different initial constraints and requirements. Keywords— MPEG, memory hierarchy, memory buffer, VHDL, FPGA