An improved algorithm-driven methodology to optimize switched current memory cells by transistor sizing

V C C I Abstract -In this paper, a design automation procedure is presented. It is an algorithm driven methodology which is capable of designing and optimizing SI circuits. we applied the proposed methodology to design optimal S21 class AB grounded gate memory cells. Owing to this procedure, this cell designed using the CMOS 0.35pm process under a single 3.3Vpower supply voltage, achieves 80 dB as dynamic range at 16 MHz sampling frequency. Besides it reaches less than 0.5 ns as settling time when priori@ is given to design high speed cells.