Package Electrical Testing

Electronic packages provide a means for interconnecting, powering, cooling, and protecting integrated-circuit (IC) chips. This is made possible through interconnections that provide a connection between active devices, such as integrated-circuit chips or to other discrete components, mounted on the package. Because semiconductor chips are expensive, a testing scheme is necessary to ensure the integrity and performance of all the package interconnection paths. This is a two-step process: final testing of the interconnection paths prior to attachment of the active devices (dies or chips) and subsequent testing of the assembled package. In this chapter, an integrated circuit in its barest form (wafer after dicing) is called a die and when it’s ready to be packaged is called a chip.

[1]  Lawrence T. Pillage,et al.  An efficient methodology for extraction and simulation of transmission lines for application specific electronic modules , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[2]  W. Blood,et al.  Electrical analysis of a thin film multichip module substrate , 1992, Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92.

[3]  J. Marshall,et al.  CAD-based net capacitance testing of unpopulated MCM substrates , 1994 .

[4]  Andy Hopper,et al.  A feasibility study for the fabrication of planar silicon multichip modules using electron beam lithography for precise location and interconnection of chips , 1992 .

[5]  M. M. Pradhan,et al.  Circular BIST with partial scan , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[6]  P. Slade,et al.  Contact resistance variations of tungsten contacts operated in air and silver-tungsten carbide contacts operated in vacuum , 1990 .

[7]  J. F. McDonald,et al.  MCM: The High-Performance Electronic Packaging Technology , 1993, Computer.

[8]  Yervant Zorian,et al.  An Effective BIST Scheme for ROM's , 1992, IEEE Trans. Computers.

[9]  L. Economikos,et al.  Electrical test of multichip substrates , 1994 .

[10]  M. Swaminathan,et al.  Design tradeoffs among MCM-C, MCM-D and MCM-D/C technologies , 1994 .

[11]  Najmi T. Jarwala,et al.  The boundary-scan master: target applications and functional requirements , 1990, Proceedings. International Test Conference 1990.

[12]  Lina Prokopchak.  Development of a solution for achieving known-good-die , 1994, Proceedings., International Test Conference.

[13]  J. M. Jong,et al.  Equivalent circuit modeling of interconnects from time domain measurements , 1992 .

[14]  Joel A. Jorgenson,et al.  Analyzing the design-for-test techniques in a multiple substrate MCM , 1994, Proceedings of IEEE VLSI Test Symposium.

[15]  A. Flint.  Testing multichip modules , 1994, IEEE Spectrum.

[16]  Abhijit Chatterjee,et al.  Fault simulation of linear analog circuits , 1993, J. Electron. Test..

[17]  Yervant Zorian,et al.  A distributed BIST control scheme for complex VLSI devices , 1993, Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium.

[18]  Sung-Mo Kang,et al.  Physical Design for Multichip Modules , 1994 .

[19]  Frank W. Angelotti.  Modeling for structured system interconnect test , 1994, Proceedings., International Test Conference.

[20]  Robert J. Wojnarowski,et al.  Bare chip test techniques for multichip modules , 1990, 40th Conference Proceedings on Electronic Components and Technology.

[21]  Keith W. Goossen,et al.  Modeling of picosecond pulse propagation in microstrip interconnections of integrated circuits , 1989 .

[22]  E. Beyne,et al.  A broad band loss model for MCM interconnections , 1993, Proceedings 1993 IEEE Multi-Chip Module Conference MCMC-93.

[23]  Madhavan Swaminathan,et al.  A novel MCM interconnect test technique based on resonator principles and transmission line theory , 1995, Proceedings of Electrical Performance of Electronic Packaging.

[24]  Lynn Roszel.  MCM foundry test methodology and implementation , 1993, Proceedings of IEEE International Test Conference - (ITC).

[25]  Najmi T. Jarwala,et al.  A new framework for analyzing test generation and diagnosis algorithms for wiring interconnects , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[26]  R. H. Parker.  Bare die test , 1992, Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92.

[27]  Abhijit Chatterjee,et al.  A novel low-cost approach to MCM interconnect test , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[28]  R. N. Schmidt,et al.  Electron-beam technology for open/short testing of multichip substrates , 1990 .

[29]  R. Imai,et al.  MCM substrate with high capacitance , 1995 .

[30]  D. C. Keezer.  Bare die testing and MCM probing techniques , 1992, Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92.

[31]  Reinhold Dipl.-Ing. Schmitt,et al.  Electron-beam MCM testing and probing , 1994 .

[32]  Thomas M. Storey,et al.  A test methodology for VLSI chips on silicon , 1993, Proceedings of IEEE International Test Conference - (ITC).

[33]  Anand Gopinath,et al.  Capacitance Parameters of Discontinuities in Microstriplines , 1978 .

[34]  Rodham E. Tulloss,et al.  The Test Access Port and Boundary Scan Architecture , 1990 .

[35]  Franc Brglez,et al.  Automatic Pattern Generation for Diagnosis of Wiring Interconnect Faults , 1992, Proceedings International Test Conference 1992.

[36]  Yervant Zorian.  A universal testability strategy for multi-chip modules based on BIST and boundary-scan , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[37]  Barbara Vasquez,et al.  Known-good-die technologies on the horizon , 1994, Proceedings of IEEE VLSI Test Symposium.

[38]  I. Wolff,et al.  A Method for Calculating the Frequency-Dependent Properties of Microstrip Discontinuities , 1977 .

[39]  Arnold Halperin,et al.  Latent open testing of electronic packaging , 1994, Proceedings of IEEE Multi-Chip Module Conference (MCMC-94).

[40]  Zhang Xiaolei,et al.  Time-domain finite difference approach to the calculation of the frequency-dependent characteristics of microstrip discontinuities , 1988 .

[41]  Marcelo Lubaszewski,et al.  A pragmatic test and diagnosis methodology for partially testable MCMs , 1994, Proceedings of IEEE Multi-Chip Module Conference (MCMC-94).

[42]  W. R. Eisenstadt,et al.  High-speed VLSI interconnect modeling based on S-parameter measurements , 1993 .

[43]  J.R. Brews,et al.  Transmission line models for lossy waveguide interconnections in VLSI , 1986, IEEE Transactions on Electron Devices.

[44]  P. Katehi,et al.  Frequency-Dependent Characteristics of Microstrip Discontinuities in Millimeter-Wave Integrated Circuits , 1985 .

[45]  D. Pozar,et al.  Full-Wave Analysis of Microstrip Open-End and Gap Discontinuities , 1985 .

[46]  T. Ueno,et al.  Membrane probe technology for MCM Known-Good-Die , 1994, Proceedings., International Test Conference.

[47]  W. David Ballew,et al.  Board-level boundary-scan: regaining observability with an additional IC , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[48]  Wojciech Maly,et al.  Are there any alternatives to "known good die" ? /spl lsqb/MCMs/spl rsqb/ , 1994, Proceedings of IEEE Multi-Chip Module Conference (MCMC-94).

[49]  Yervant Zorian,et al.  Built-in self-test for digital integrated circuits , 1994, AT&T Technical Journal.

[50]  S. M. Defoster,et al.  Automatic testing of metallized ceramic-polyimide (MCP) substrates , 1990 .

[51]  William H. Kautz,et al.  Testing for Faults in Wiring Networks , 1974, IEEE Transactions on Computers.

[52]  Abhijit Chatterjee,et al.  Fault-based automatic test generator for linear analog circuits , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[53]  A. H. Landzberg,et al.  Microelectronics manufacturing diagnostics handbook , 1993 .

[54]  Andrew William Ross,et al.  High density interconnect verification using voltage contrast electron beam , 1991, [1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium.

[55]  Stephen C. Hilla.  Boundary scan testing for multichip modules , 1992, Proceedings International Test Conference 1992.

[56]  Kenneth E. Posse.  A DESIGN-FOR-TESTABILITY ARCHITECTURE FOR MULTICHIP MODULES , 1991, 1991, Proceedings. International Test Conference.

[57]  D. R. Barbour,et al.  Thermal conduction module: a high-performance multilayer ceramic package , 1982 .

[58]  Thomas M. Storey,et al.  A test methodology to support an ASEM MCM foundry , 1994, Proceedings., International Test Conference.

[59]  Eric D. Perfecto,et al.  Large format fabrication-a practical approach to low cost MCM-D , 1995 .

[60]  O. C. Woodard.  High density interconnect verification of unpopulated multichip modules , 1991, [1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium.

[61]  Andrew Flint.  Test strategies for a family of complex MCMs , 1994, Proceedings., International Test Conference.

[62]  Brendan Davis.  The Economics of Automatic Testing , 1982 .

[63]  T. Sakata,et al.  Prober for highly integrated multichip modules , 1991, [1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium.

[64]  Y. Zorian.  A structured approach to macrocell testing using built-in self-test , 1990, IEEE Proceedings of the Custom Integrated Circuits Conference.

[65]  A. Deutsch,et al.  Characterization of resistive transmission lines by short-pulse propagation , 1992, IEEE Microwave and Guided Wave Letters.

[66]  Lawrence T. Pileggi,et al.  RICE: rapid interconnect circuit evaluation using AWE , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[67]  John H. Lau,et al.  Chip on Board: Technologies for Multichip Modules , 1995 .

[68]  Chung-Kuan Cheng,et al.  A multi-probe approach for MCM substrate testing , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[69]  John U. Knickerbocker,et al.  IBM System/390 air-cooled alumina thermal conduction module , 1991, IBM J. Res. Dev..

[70]  E. J. Rymaszewski,et al.  Microelectronics Packaging Handbook , 1988 .

[71]  Robert C. Block,et al.  Noncontact testing of circuits via a laser-induced plasma electrical pathway , 1992, IEEE Design & Test of Computers.

[72]  J. L. Prince,et al.  Crosstalk analysis for high-speed pulse propagation in lossy electrical interconnections , 1993 .

[73]  H. Hesselbom,et al.  Investigation of high-speed pulse transmission in MCM-D , 1993 .

[74]  Yervant Zorian,et al.  PSBIST: A partial-scan based built-in self-test scheme , 1993, Proceedings of IEEE International Test Conference - (ITC).

[75]  Abhijit Chatterjee,et al.  MIXER: Mixed-signal fault simulator , 1993, Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93.

[76]  A. Deutsch,et al.  Factors affecting the interconnection resistance and yield in multilayer polyimide/copper structures , 1993 .

[77]  Tatsuo Itoh,et al.  Generalized Scattering Matrix Method for Analysis of Cascaded and Offset Microstrip Step Discontinuities , 1986 .

[78]  Roy Knowles,et al.  Automatic testing: Systems and applications , 1976 .

[79]  S. Rusu,et al.  SuperSPARC multichip module , 1993, Proceedings 1993 IEEE Multi-Chip Module Conference MCMC-93.