Economic Aspects of Memory Built-in Self-Repair

With the advent of deep-submicron technology and SoC design methodology, it's possible to integrate heterogeneous cores from different sources in a single chip containing millions of gates. The yield of such a large chip is usually too low to be profitable. Therefore, yield enhancement is an important issue in SoC product development. Memory cores usually occupy a large proportion of the area of a typical SoC, and they normally have higher circuit density, so they tend to dominate SoC yield. This article presents cost and benefit models to evaluate the economic effectiveness of typical memory BISR implementations. Experimental results with a simulator based on these cost models show that memory size impacts cost-effectiveness more than production volume does.

[1]  Cheng-Wen Wu,et al.  MRAM defect analysis and fault modeling , 2004, 2004 International Conferce on Test.

[2]  Nadir Achouri,et al.  Optimal reconfiguration functions for column or data-bit built-in self-repair , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[3]  Takayasu Sakurai,et al.  Built-in self-repair circuit for high-density ASMIC , 1989, 1989 Proceedings of the IEEE Custom Integrated Circuits Conference.

[4]  Jin-Fu Li,et al.  A simulator for evaluating redundancy analysis algorithms of repairable embedded memories , 2002, Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002).

[5]  Yervant Zorian,et al.  Embedded-memory test and repair: infrastructure IP for SoC yield , 2003, IEEE Design & Test of Computers.

[6]  Yervant Zorian.  Embedding infrastructure IP for SOC yield improvement , 2002, DAC '02.

[7]  Cheng-Wen Wu,et al.  Cost and benefit models for logic and memory BIST , 2000, DATE '00.

[8]  Hideto Hidaka,et al.  A built-in self-repair analyzer (CRESTA) for embedded DRAMs , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[9]  M. Nicolaidis,et al.  Dynamic Data-bit Memory Built-In Self- Repair , 2003, ICCAD 2003.

[10]  Alfredo Benso,et al.  An on-line BIST RAM architecture with self-repair capabilities , 2002, IEEE Trans. Reliab..

[11]  Jin-Fu Li,et al.  A built-in self-repair scheme for semiconductor memories with 2-d redundancy , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[12]  Jin-Fu Li,et al.  Built-in redundancy analysis for memory yield improvement , 2003, IEEE Trans. Reliab..

[13]  Yervant Zorian.  Embedded Memory Test & Repair : Infrastructure IP for SOC Yield Yervant Zorian Virage Logic , 2002 .

[14]  Robert Aitken.  A modular wrapper enabling high speed BIST and repair for small wide memories , 2004 .

[15]  Yervant Zorian,et al.  Built in self repair for embedded high density SRAM , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).