Novel Three Dimensional (3D) NAND Flash Memory Array Having Tied Bit-line and Ground Select Transistor (TiGer)

In this paper, a three dimensional (3D) NAND flash memory array having Tied Bit-line and Ground Select Transistor (TiGer) is investigated. Bit-lines are stacked in the vertical direction to increase the memory density without the device size scaling. To distinguish stacked bit-lines, a novel operation scheme is introduced instead of adding supplementary control gates. The stacked layers are selected by using ground select line (GSL) and common source line (CSL). Device structure and fabrication process are described. Operation scheme and simulation results for program inhibition are also discussed. Keyword 3 dimensional NAND flash memory, operation scheme, program inhibition.