System-Level Synthesis for Wireless Sensor Node Controllers: A Complete Design Flow

Wireless sensor networks (WSN) is a new and very challenging research field for embedded system design automation. Engineering a WSN node hardware platform is known to be a tough challenge, as the design must enforce many severe constraints, among which energy dissipation is by far the most important one. WSN node devices have until now been designed using off-the-shelf low-power microcontroller units (MCUs), even if their power dissipation is still an issue and hinders the widespread use of this new technology. In this work, we propose a complete system-level flow for an alternative approach based on the concept of hardware microtasks, which relies on hardware specialization and power gating to drastically improve the energy efficiency of the computational/control part of the node. Our case study shows that power savings between one to two orders of magnitude are possible w.r.t. MCU-based implementations.

[1]  Daniel Gajski,et al.  Generic Architecture Description for Retargetable Compilation and Synthesis of Application-Specific Pipelined IPs , 2006, 2006 International Conference on Computer Design.

[2]  Daeyeon Kim,et al.  The Phoenix Processor: A 30pW platform for sensor applications , 2008, 2008 IEEE Symposium on VLSI Circuits.

[3]  Philip Levis,et al.  Usenix Association 8th Usenix Symposium on Operating Systems Design and Implementation 323 Quanto: Tracking Energy in Networked Embedded Systems , 2022 .

[4]  Nikil D. Dutt,et al.  SPARK: a high-level synthesis framework for applying parallelizing compiler transformations , 2003, 16th International Conference on VLSI Design, 2003. Proceedings..

[5]  Philip Alexander Levis.  TinyOS: An Open Operating System for Wireless Sensor Networks (Invited Seminar) , 2006, 7th International Conference on Mobile Data Management (MDM'06).

[6]  David E. Culler,et al.  Versatile low power media access for wireless sensor networks , 2004, SenSys '04.

[7]  David E. Culler,et al.  TinyOS: An Operating System for Sensor Networks , 2005, Ambient Intelligence.

[8]  Jeff Rose,et al.  MANTIS OS: An Embedded Multithreaded Operating System for Wireless Micro Sensor Platforms , 2005, Mob. Networks Appl..

[9]  Gu-Yeon Wei,et al.  An accelerator-based wireless sensor network processor in 130nm CMOS , 2009, CASES '09.

[10]  Frederic T. Chong,et al.  Exploring the Processor and ISA Design for Wireless Sensor Network Applications , 2008, 21st International Conference on VLSI Design (VLSID 2008).

[11]  Olivier Sentieys,et al.  Ultra low-power FSM for control oriented applications , 2009, 2009 IEEE International Symposium on Circuits and Systems.

[12]  A.P. Chandrakasan,et al.  A 65 nm Sub-$V_{t}$ Microcontroller With Integrated SRAM and Switched Capacitor DC-DC Converter , 2008, IEEE Journal of Solid-State Circuits.

[13]  Ian F. Akyildiz,et al.  Wireless sensor networks: a survey , 2002, Comput. Networks.

[14]  David E. Culler,et al.  Design of a wireless sensor network platform for detecting rare, random, and ephemeral events , 2005, IPSN 2005. Fourth International Symposium on Information Processing in Sensor Networks, 2005..

[15]  Pradip Bose,et al.  Microarchitectural techniques for power gating of execution units , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

[16]  Adam Dunkels,et al.  Contiki - a lightweight and flexible operating system for tiny networked sensors , 2004, 29th Annual IEEE International Conference on Local Computer Networks.

[17]  R. Engelbrecht,et al.  DIGEST of TECHNICAL PAPERS , 1959 .

[18]  Kurt Keutzer,et al.  Instruction selection using binate covering for code size optimization , 1995, ICCAD.

[19]  Jan M. Rabaey,et al.  Power-efficient rendez-vous schemes for dense wireless sensor networks , 2004, 2004 IEEE International Conference on Communications (IEEE Cat. No.04CH37577).

[20]  Santanu Chattopadhyay,et al.  Integrated Power-Gating and State Assignment for Low Power FSM Synthesis , 2008, 2008 IEEE Computer Society Annual Symposium on VLSI.

[21]  Jan M. Rabaey,et al.  Energy Scavenging for Wireless Sensor Networks: with Special Focus on Vibrations , 2012 .

[22]  Chris J. Bleakley,et al.  Low-power TinyOS tuned processor platform for wireless sensor network motes , 2010, TODE.

[23]  Lei He,et al.  Distributed sleep transistor network for power reduction , 2003, DAC '03.

[24]  Daniel Gajski,et al.  Automatic architecture refinement techniques for customizing processing elements , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[25]  Saraju P. Mohanty,et al.  Low-Power High-Level Synthesis for Nanoscale CMOS Circuits , 2008 .

[26]  J. Rabaey,et al.  A Power-Managed Protocol Processor for Wireless Sensor Networks , 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..

[27]  François Charot,et al.  Constraint-Driven Instructions Selection and Application Scheduling in the DURASE system , 2009, 2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors.

[28]  Luca Benini,et al.  Post-layout leakage power minimization based on distributed sleep transistor insertion , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

[29]  Ludovic L'Hours.  Generating efficient custom FPGA soft-cores for control-dominated applications , 2005, 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05).

[30]  Mark A. Shayman,et al.  Energy Efficient Routing in Wireless Sensor Networks , 2003 .

[31]  SentieysOlivier,et al.  System-Level Synthesis for Wireless Sensor Node Controllers , 2012 .

[32]  M. Minuth,et al.  SenseBench: toward an accurate evaluation of sensor network processors , 2005, IEEE International. 2005 Proceedings of the IEEE Workload Characterization Symposium, 2005..

[33]  Mani Srivastava,et al.  Energy efficient routing in wireless sensor networks , 2001, 2001 MILCOM Proceedings Communications for Network-Centric Operations: Creating the Information Force (Cat. No.01CH37277).

[34]  Christopher W. Fraser,et al.  BURG: fast optimal instruction selection and tree parsing , 1992, SIGP.

[35]  Rajit Manohar,et al.  An ultra low-power processor for sensor networks , 2004, ASPLOS XI.

[36]  Dinesh,et al.  System Architecture Directions for Networked Sensors , 2014 .

[37]  Jason Cong,et al.  Synthesis of an application-specific soft multiprocessor system , 2007, FPGA '07.

[38]  Olivier Berder,et al.  Cooperative MIMO Schemes Optimal Selection for Wireless Sensor Networks , 2007, 2007 IEEE 65th Vehicular Technology Conference - VTC2007-Spring.

[39]  Robert Szewczyk,et al.  System architecture directions for networked sensors , 2000, ASPLOS IX.

[40]  Franco Fummi,et al.  Soft-cores generation by instruction set analysis , 2001, International Symposium on System Synthesis (IEEE Cat. No.01EX526).

[41]  Mani Srivastava,et al.  Energy-aware wireless microsensor networks , 2002, IEEE Signal Process. Mag..

[42]  Hai Zhou,et al.  Parallel CAD: Algorithm Design and Programming Special Section Call for Papers TODAES: ACM Transactions on Design Automation of Electronic Systems , 2010 .