Dynamic wordlength calibration to reduce power dissipation in wireless OFDM systems

This paper describes low power architecture by using a dynamic wordlength technique in wireless orthogonal frequency division multiplexing (OFDM) system. The number of wordlength in digital signal processing (DSP) has to be carefully determined because wordlength affects system performance and hardware cost. Dynamic wordlength technique is applied to a fast Fourier transform (FFT) processor and a Viterbi decoder in OFDM receiver. The proposed method searches an optimum wordlength combination of FFT processor and Viterbi decoder by comparing output binary data while changing wordlengths. This operation is done by use of intervals in packet waiting. This approach leads to achieve the power reduction up to 23.9% with a desirable packet error rate (PER) in multipath channel environment.

[1]  Yoshikazu Miyanaga,et al.  Use of a Variable Wordlength Technique in an OFDM Receiver to Reduce Energy Dissipation , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[2]  Yoshikazu Miyanaga,et al.  Design of variable wordlength Viterbi decoder in BICM-OFDM systems , 2009, 2009 9th International Symposium on Communications and Information Technology.

[3]  John Terry,et al.  OFDM Wireless LANs: A Theoretical and Practical Guide , 2001 .

[4]  H. Yasuura,et al.  A design method for a low power equalization circuit by adaptive bitwidth control , 2004, IEEE International Symposium on Communications and Information Technology, 2004. ISCIT 2004..

[5]  A. M. Abdullah,et al.  Wireless lan medium access control (mac) and physical layer (phy) specifications , 1997 .

[6]  Brian L. Evans,et al.  Wordlength optimization with complexity-and-distortion measure and its application to broadband wireless demodulator design , 2004, 2004 IEEE International Conference on Acoustics, Speech, and Signal Processing.

[7]  Shousheng He,et al.  Design and implementation of a 1024-point pipeline FFT processor , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

[8]  Yoshikazu Miyanaga,et al.  Tunable Wordlength Architecture for a Low Power Wireless OFDM Demodulator , 2006, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

[9]  Luca Benini,et al.  Saving power by synthesizing gated clocks for sequential circuits , 1994, IEEE Design & Test of Computers.