Multiple-valued radix-2 signed-digit arithmetic circuits for high-performance VLSI systems
暂无分享,去创建一个
[1] Michitaka Kameyama,et al. A 32 × 32 BIT multiplier using multiple-valued MOS current-mode circuits , 1987, 1987 Symposium on VLSI Circuits.
[2] Shoji Kawahito,et al. A multiplier chip with multiple-valued bidirectional current-mode logic circuits , 1988, Computer.
[3] Algirdas Avizienis,et al. Signed-Digit Numbe Representations for Fast Parallel Arithmetic , 1961, IRE Trans. Electron. Comput..
[4] H. Yoshimura,et al. A 50mhz Cmos Geometrical Mapping Processor , 1988, 1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers.
[5] Yutaka Hayashi,et al. Diffusion Selfaligned MOST; A New Approach for High Speed Device , 1969 .
[6] Hiroto Yasuura,et al. High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree , 1985, IEEE Transactions on Computers.
[7] H. Edamatsu,et al. A 33 Mflops Floating Point Processor Using Redundant Binary Representation , 1988, 1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers.
[8] S. Kawahito,et al. VLSI-oriented bi-directional current-mode arithmetic circuits based on the Radix-4 signed-digit number system , 1986 .
[9] M. Kameyama,et al. High-performance multiple-valued radix-2 signed-digit multiplier and its application , 1989, Symposium 1989 on VLSI Circuits.
[10] Hironori Yamauchi,et al. A 50-MHz CMOS geometrical mapping processor , 1989 .
[11] Louis P. Rubinfield. A Proof of the Modified Booth's Algorithm for Multiplication , 1975, IEEE Transactions on Computers.
[12] J. Greene,et al. A CMOS 32b Wallace tree multiplier-accumulator , 1986, 1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[13] Masakazu Yamashina,et al. 200 MHz 16-bit BiCMOS signal processor , 1989, IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers.