Hardware accelerated power estimation

In this paper, we present power emulation, a novel design paradigm that utilizes hardware acceleration for the purpose of fast power estimation. Power emulation is based on the observation that the functions necessary for power estimation (power model evaluation, aggregation, etc.) can be implemented as hardware circuits. Therefore, we can enhance any given design with "power estimation hardware", map it to a prototyping platform, and exercise it with any given test stimuli to obtain power consumption estimates. Our empirical studies with industrial designs reveal that power emulation can achieve significant speedups (10X to 500X) over state-of-the-art commercial register-transfer level (RTL) power estimation tools.

[1]  Massoud Pedram,et al.  High-level Power Modeling, Estimation, And Optimization , 1997, Proceedings of the 34th Design Automation Conference.

[2]  Radu Marculescu,et al.  Information theoretic measures of energy consumption at register transfer level , 1995, ISLPED '95.

[3]  Sujit Dey,et al.  High-Level Power Analysis and Optimization , 1997 .

[4]  Anantha P. Chandrakasan,et al.  Low Power Digital CMOS Design , 1995 .

[5]  Massoud Pedram,et al.  Low power design methodologies , 1996 .

[6]  Kazutoshi Wakabayashi,et al.  C - based high - level synthesis system, CYBER - Design experience , 2000 .

[7]  Srivaths Ravi,et al.  Efficient RTL power estimation for large designs , 2003, 16th International Conference on VLSI Design, 2003. Proceedings..

[8]  Kees G. W. Goossens,et al.  The Petrol approach to high-level power estimation , 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

[9]  Luca Benini,et al.  Regression Models for Behavioral Power Estimation , 1998, Integr. Comput. Aided Eng..