Write and Erase Threshold Voltage Interdependence in Resistive Switching Memory Cells

A statistical dependence of set voltage Vset on the preceding reset voltage Vreset is observed in resistive memory arrays and explained in terms of two interlocking mechanisms. This dependence can be replicated on a single device by intentionally varying Vreset values by various linear voltage ramp rates. The latter mechanism is well modeled under the assumption that a critical heat deposited locally in the filament triggers the rupture of the filament. Mechanisms are proposed to explain the impact of different ramp rates of the reset operation on the ruptured gap in the filament that affect, in turn, the Vset value of the subsequent set operation. Based on these observations, a one-time tightening procedure is designed, leading to tightened Vset and Vreset distributions.

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