Data flow chip ImPP and its system for image processing

A data flow image pipelined processor VLSI chip (ImPP:µPD7281) has been developed. Its hardware architecture and the experimental Template Controlled Image Processing System -3 (TIP-3), which includes 8 ImPP chips, are described. The ImPP is characterized by its data flow architecture and flexible pipeline processing. The ImPP has a uni-directional pipeline bus. The connection between ImPPs is easy and does not require extra circuits. The processing performance can be increased by connecting many chips to each other. In this multiple ImPP configuration, individual ImPPs share different portions of the pipeline programs and different portions of spatial data. The ImPP can be used in various system configurations. A single ImPP chip is sufficient for simple processing and multiple ImPPs are useful for a faster image processing system. Performance estimation using a software simulator, and also using an actual hardware system has been carried out. TIP-3's top performance is 40 MIPS. The main factors which influence execution efficiency are discussed and analyzed.