Power driven partial scan

The power consumption and testability are two of major considerations in modern VLSI design. A full-scan method had been used widely in the past to improve the testability of sequential circuits. Due to the lower overheads incurred, the partial-scan design has gradually become popular. The authors propose a partial scan selection strategy that bases on the structural analysis approach and considers the area and power overheads simultaneously. A powerful sample-and-search algorithm is used to find the solution that minimizes the user-specified cost function in term of power and area overheads. The experimental results show that the sample-and-search algorithm can effectively find the best solution of the specified cost function for almost all circuits, and the saving of overheads on average for each specific cost function is significant.

[1]  Rabindra K. Roy,et al.  The Best Flip-Flops to Scan , 1991, 1991, Proceedings. International Test Conference.

[2]  José C. Monteiro,et al.  A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits , 1994, 31st Design Automation Conference.

[3]  Melvin A. Breuer,et al.  BALLAST: a methodology for partial scan design , 1989, [1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

[4]  Ibrahim N. Hajj,et al.  Power Estimation in Sequential Circuitsy , 1995, 32nd Design Automation Conference.

[5]  Chi-Ying Tsui,et al.  Exact and Approximate Methods for Calculating Signal and Transition Probabilities in FSMs , 1994, 31st Design Automation Conference.

[6]  Vishwani D. Agrawal,et al.  An economical scan design for sequential logic test generation , 1989, [1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

[7]  S.M. Reddy,et al.  On determining scan flip-flops in partial-scan designs , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[8]  Hanoch Levy,et al.  A Contraction Algorithm for Finding Small Cycle Cutsets , 1988, J. Algorithms.

[9]  Kaushik Roy,et al.  Estimation of sequential circuit activity considering spatial and temporal correlations , 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.

[10]  Kurt Keutzer,et al.  Estimation of average switching activity in combinational and sequential circuits , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[11]  Janak H. Patel,et al.  An optimization based approach to the partial scan design problem , 1990, Proceedings. International Test Conference 1990.

[12]  Tan-Li Chou,et al.  Statistical estimation of sequential circuit activity , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[13]  Farid N. Najm,et al.  Power estimation techniques for integrated circuits , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[14]  Chih-Chang Lin,et al.  Cost-free scan: a low-overhead scan path design methodology , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[15]  Janak H. Patel,et al.  A fault oriented partial scan design approach , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[16]  Kwang-Ting Cheng,et al.  Timing-driven partial scan , 1995 .