Easily Testable Realization Based on Single-Rail-Input OR-AND-EXOR Expressions

It is known that AND-EXOR two-level networks obtained by AND-EXOR expressions with positive literals are easily testable. They are based on the single-rail-input logic, and require (n + 4) tests to detect their single stuck-at faults, where n is the number of the input variables. We present three-level networks obtained from single-rail-input OR-ANDEXOR expressions and propose a more easily testable realization than the AND-EXOR networks. The realization is an OR-ANDEXOR network which limits the fan-in of the AND and OR gates to n/r and r respectively, where r is a constant (1 ≤ r ≤ n). We show that only (r + n/r) tests are required to detect the single stuck-at faults by adding r extra variables to the network. key words: logic synthesis, exclusive-or, single stuck-at fault, easily testable realization

[1]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[2]  Dhiraj K. Pradhan,et al.  Universal Test Sets for Multiple Fault Detection in AND-EXOR Arrays , 1978, IEEE Transactions on Computers.

[3]  Tsutomu Sasao,et al.  Minimization of AND-OR-EXOR Three-Level Networks with AND Gate Sharing (Special Issue on Synthesis and Verification of Hardware Design) , 1997 .

[4]  Tsutomu Sasao.  Logic Synthesis with Exor Gates , 1993 .

[5]  SUDHAKAR M. REDDY,et al.  Easily Testable Realizations ror Logic Functions , 1972, IEEE Transactions on Computers.

[6]  Marek Perkowski,et al.  Fixed-Polarity AND/XOR Canonical Networks , 1992 .

[7]  J. A. Salvato.  John wiley & sons. , 1994, Environmental science & technology.

[8]  Tsutomu Sasao.  Easily testable realizations for generalized Reed-Muller expressions , 1994, Proceedings of IEEE 3rd Asian Test Symposium (ATS).

[9]  Sudhakar M. Reddy,et al.  Fault Detecting Test Sets for Reed-Muller Canonic Networks , 1975, IEEE Transactions on Computers.

[10]  Kensuke Shimizu,et al.  Easily testable realization based on OR-AND-EXOR expansion with single rail inputs , 1998, IEEE. APCCAS 1998. 1998 IEEE Asia-Pacific Conference on Circuits and Systems. Microelectronics and Integrating Systems. Proceedings (Cat. No.98EX242).

[11]  Tsutomu Sasao.  Optimization of Pseudo-Kronecker Expressions Using Multiple-Place Decision Diagrams , 1993 .