Elimination of dead-time transients in a three-level flying capacitor inverter using a state machine for switching state sequence selection

In a three-level flying capacitor inverter, certain switching state sequences can cause an undesirable transient in the pole voltage. The transients constitute and error voltage which degrades harmonic performance, distorts the current and generates electromagnetic noise. This paper presents a scheme to completely eliminate these dead-time transients using a digital state machine to determine the switching state to be applied in the subsequent switching period based on the present switching state. The modified switching state does not change the effective phase voltage, and the floating capacitors are kept well balanced. The proposed scheme works independent of the modulation or control scheme in use. The scheme was first tested in simulation, followed by deployment on an FPGA for hardware validation and timing analysis.