A novel 18 GHz 1.3 mW CMOS frequency divider with high input sensitivity

A novel CMOS high speed divide-by-two circuit with very low power consumption is proposed in this paper. The circuit features very low input capacitance and a wide locking range of 1.5-18 GHz with a power consumption of less than 1.3 mW at 1.8 V. The input sensitivity of the stage is improved significantly when compared to conventional dynamic loaded high frequency dividers. The concept and design issue of the circuit is presented together with a performance comparison to existing topologies. The idea is demonstrated and verified in a standard 0.18 /spl mu/m CMOS process through realistic simulations originating from a complete layout using moderately extracted parasitics.

[1]  S. Pellerano,et al.  Phase noise in digital frequency dividers , 2004, IEEE Journal of Solid-State Circuits.

[2]  Ran-Hong Yan,et al.  A 13.4-GHz CMOS frequency divider , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

[3]  Jri Lee,et al.  A 40-GHz frequency divider in 0.18-/spl mu/m CMOS technology , 2004, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).

[4]  W.F. Egan,et al.  Modeling phase noise in frequency dividers , 1990, IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control.

[5]  T. Lee,et al.  Superharmonic injection-locked frequency dividers , 1999, IEEE J. Solid State Circuits.

[6]  K.A. Jenkins,et al.  A 26.5 GHz silicon MOSFET 2:1 dynamic frequency divider , 2000, IEEE Microwave and Guided Wave Letters.

[7]  M. Fujishima,et al.  1V 2GHz CMOS frequency divider , 2003 .

[8]  H.-D. Wohlmuth,et al.  A high sensitivity static 2:1 frequency divider up to 27GHz in 120nm CMOS , 2002, Proceedings of the 28th European Solid-State Circuits Conference.