Low energy 16-bit Booth leapfrog array multiplier using dynamic adders

The paper presents a low-voltage (1–1.5 V) 16-bit Booth leapfrog array multiplier with emphasis on low energy dissipation, relatively high speed and small IC area. These attributes are achieved in two ways. First, low (hardware) complexity dynamic adders (DAs) are proposed and they are used to reduce spurious switching in the multiplier. Second, the specificities of the leapfrog architecture are exploited with the use of different output rates of the sum and carry outputs of the proposed DAs. When compared with other array multiplier designs, the proposed multiplier features the lowest energy dissipation and one of the shortest delays, resulting in the lowest energy–delay product. Furthermore, when compared with the reported dynamic array multiplier that features somewhat similar electrical characteristics, the proposed multiplier is advantageous in its substantially smaller (∼33%) IC area. Based on a 0.35 µm dual-poly four-metal CMOS process and at 1 V operation, the proposed multiplier dissipates ∼18 pJ, has a delay of ∼188 ns and occupies 0.11 mm2 of IC area. The proposed design is appropriate for low-voltage energy-critical and IC area-critical applications including hearing aids.

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