The Performance Evaluation of Link-Sharing Method of Buffer in NoC Router

We have proposed a memory sharing method of the wormhole routed network-on-chip architecture. In our method, a memory is shared between multiple physical links by using the multi-port memory. We evaluate and discuss the communication performance in the various situations. It is shown that the minimum number of memory banks required in multiport memory for 2D-torus and 2D-mesh networks is 8. Our proposed method yields high performance for both torus and mesh networks. Even this high performance is retained when the buffer size and the packet length are same.

[1]  Yuval Tamir,et al.  The design and implementation of a multiqueue buffer for VLSI communication switches , 1989, Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[2]  Shigeyoshi Watanabe,et al.  Link-sharing method of buffer in direct-connection network , 2011, Proceedings of 2011 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing.

[3]  Niraj K. Jha,et al.  A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS , 2007, ICCD.

[4]  T. Gyohten,et al.  Area-Efficient Multi-Port SRAMs for On-Chip Data-Storage with High Random-Access Bandwidth and Large Storage Capacity , 2001 .

[5]  Yuval Tamir,et al.  Dynamically-Allocated Multi-Queue Buffers for VLSI Communication Switches , 1992, IEEE Trans. Computers.

[6]  Pierre Fraigniaud,et al.  A General Theory for Deadlock Avoidance in Wormhole-Routed Networks , 1998, IEEE Trans. Parallel Distributed Syst..

[7]  Lionel M. Ni,et al.  A survey of wormhole routing techniques in direct networks , 1993, Computer.

[8]  Ali Ahmadinia,et al.  A Highly Adaptive and Efficient Router Architecture for Network-on-Chip , 2011, Comput. J..

[9]  Bill Lin,et al.  Extending the Effective Throughput of NoCs With Distributed Shared-Buffer Routers , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  William J. Dally,et al.  Virtual-channel flow control , 1990, [1990] Proceedings. The 17th Annual International Symposium on Computer Architecture.