Josephson modified variable threshold logic gates for use in ultra-high-speed LSI

A gate family called modified variable threshold logic (MVTL) is proposed. The OR gate is a two-junction interferometer with one magnetically coupled control line. Magnetic coupling and current injection are used to switch the logic state of the gate. By optimizing the gate parameters, an operating margin of +or-43% and a switching speed of 2.5 ps/gate are obtained. the gate area is 30 mu m*24 mu m with a 1.5- mu m minimum junction diameter. The gate family consists of an OR gate, a single-junction AND gate, and a timed inverter (TI) that consists of the OR gate, a junction, and resistors. The delay time of the gate operated in the actual circuit was found to be less than 10 ps. Circuits having up to 1000 gates, the critical path model of a 16-bit*16-bit multiplier, and a 16-bit arithmetic logic unit have been successfully operated. When the Josephson gate is operated with three-phase power, it is possible to construct any sequential circuit without the complex latch circuit required to prevent the race condition for one- or two-phase power supplies. >

[1]  Masahiro Aoyagi,et al.  High speed logic operations of all refractory Josephson integrated circuits , 1983 .

[2]  A. Shoji,et al.  High quality Nb/Al‐AlOx/Nb Josephson junction , 1985 .

[3]  S. Tahara,et al.  Logic delays of 5‐μm resistor coupled Josephson logic , 1982 .

[4]  Shinya Hasuo,et al.  Switching-Time Measurements on Josephson Variable Threshold Logic Gate , 1983 .

[5]  K. Lofstrom,et al.  Josephson logic circuit with a sinusoidal current supply , 1977 .

[6]  T. A. Fulton,et al.  B.S.T.J. Brief: A Josephson parallel multiplier , 1982, The Bell System Technical Journal.

[7]  Junichi Nakano,et al.  3.0 ps switching operation in all-Nb Josephson logic gates , 1987 .

[8]  E. Harris,et al.  Punchthrough in Josephson logic devices , 1981 .

[9]  S. Hasuo,et al.  Experimental investigations and analysis for high-quality Nb/Al-AlOx/Nb Josephson junctions , 1987 .

[10]  S. Kotani,et al.  A 3.3-ps Josephson or gate with Niobium junctions , 1986, 1986 International Electron Devices Meeting.

[11]  A. Shoji,et al.  An integration of all refractory Josephson logic LSI circuit , 1985 .

[12]  S. Kotani,et al.  High-speed unit-cell for Josephson LSI circuits using Nb/AlO x /Nb junctions , 1987 .

[13]  T. Tanaka,et al.  Proposal of dual-powered superconducting logic circuits , 1985 .

[14]  A. Mukherjee,et al.  High performance data processing in Josephson technology , 1982, IEEE Electron Device Letters.

[15]  Hirotaka Tamura,et al.  Fabrication technology for lead-alloy Josephson devices for high-density integrated circuits , 1986 .

[16]  K. Hohkawa,et al.  A Josephson dual-phase ac-powered logic network using special latch circuits , 1985, IEEE Transactions on Electron Devices.

[17]  W. Chang,et al.  The inductance of a superconducting strip transmission line , 1979 .

[18]  J. Sone,et al.  A 280-ps Josephson 4-bitx4-bit parallel multiplier , 1985, IEEE Journal of Solid-State Circuits.

[19]  S. Hasuo,et al.  A 2.5-ps Josephson or gate , 1987, 1987 International Electron Devices Meeting.

[20]  Shin-Shem Pei.  Logic delays of 5‐μm current‐switched Josephson gates , 1982 .

[21]  S. Hasuo,et al.  Characteristics of a counter-electrode coupled logic gate using Josephson junctions , 1981 .

[22]  T. Van Duzer,et al.  Miniaturization of Josephson logic circuits , 1985 .

[23]  J. X. Przybysz,et al.  Josephson data latch for frequency agile shift registers , 1987 .

[24]  H. Hayakawa,et al.  A Josephson Counter-Circuit with Two-Phase Power Supply , 1985 .

[25]  U. Kawabe,et al.  A 4b × 4b multiplier and 3b counter in Josephson threshold logic , 1986, 1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[26]  S. Kotani,et al.  9 ps Gate Delay Josephson OR Gate with Modified Variable Threshold Logic , 1985 .

[27]  Bernard Plaçais,et al.  Turn-on delay for Josephson logic devices with high damping , 1982 .

[28]  J. Magerlein,et al.  Specific capacitance of Josephson tunnel junctions , 1981 .

[29]  Yoshinobu Tarutani,et al.  Ultrahigh speed direct coupled logic gate fabricated with NbN/Pb Josephson junctions , 1984 .

[30]  Takeshi Imamura,et al.  Josephson pseudorandom bit-sequence generator , 1988 .

[31]  Hirotaka Tamura,et al.  Material Dependence of Initial Failure Rates of Josephson Junctions , 1986 .

[32]  T. A. Fulton,et al.  Observation of flux trapping threshold in narrow superconducting thin films , 1982 .

[33]  Masahiro Aoyagi,et al.  All Niobium Nitride Josephson Junction with Hydrogenated Amorphous Silicon Barrier and its Application to the Logic Circuit , 1984 .

[34]  C. Hamilton,et al.  100 GHz Binary counter based on DC SQUID's , 1982, IEEE Electron Device Letters.

[35]  S. Hasuo,et al.  A Josephson 4b Microprocessor , 1988, 1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers.

[36]  D. G. McDonald,et al.  Picosecond applications of Josephson junctions , 1980, IEEE Transactions on Electron Devices.

[37]  T. Gheewala,et al.  Moat-guarded Josephson SQUIDs , 1983 .

[38]  T.R. Gheewala,et al.  AC powered Josephson latch circuits , 1982, IEEE Journal of Solid-State Circuits.

[39]  Kohji Hohkawa,et al.  Sub-10 ps high-gain direct coupled Josephson logic gate , 1983 .

[40]  Hisao Hayakawa,et al.  Operating Characteristics of Josephson Four-Junction Logic (4JL) Gate , 1982 .

[41]  H. Abe,et al.  High speed four-bit full adder with resistor coupled Josephson logic , 1983, 1983 International Electron Devices Meeting.

[42]  N. Fujimaki,et al.  Feasibility of an ultra-high-speed Josephson multiplier , 1987 .

[43]  Hisao Hayakawa,et al.  Sub-10 ps Logic Operations in Josephson Four-Junction Logic (4JL) Gates , 1983 .

[44]  D. Herrell,et al.  Regulated AC power for Josephson interferometer latching logic circuits , 1979 .

[45]  C. Hamilton,et al.  Analog measurement applications for high speed Josephson switches , 1981 .

[46]  H. Suzuki,et al.  A parallel full adder circuit using Josephson junctions , 1981, IEEE Journal of Solid-State Circuits.

[47]  E. Harris.  Turn-on delay of Josephson interferometer logic devices , 1979 .

[48]  S. Kotani,et al.  Josephson 8-bit shift register , 1987 .

[49]  J. Sone,et al.  A high-speed four-bit full adder with a resistor coupled Josephson logic , 1983, IEEE Electron Device Letters.

[50]  T. Imamura,et al.  Application of sputtered SiO2 insulator to Nb/AlOx/Nb Josephson junctions , 1987 .

[51]  T. Van Duzer.  Josephson Digital Devices and Circuits , 1980 .

[52]  T. Duzer,et al.  Low-probability punchthrough in Josephson junctions , 1981 .

[53]  H. Hayakawa,et al.  A New Josephson Timed Inverter with Four-Junction Logic (4JL) Gate , 1983 .

[54]  H. Huggins,et al.  High quality refractory Josephson tunnel junctions utilizing thin aluminum layers , 1983 .

[55]  S. Kotani,et al.  Ultrahigh-speed logic gate family with Nb/Al-AlOx/Nb Josephson junctions , 1986, IEEE Transactions on Electron Devices.

[56]  Hisao Hayakawa.  Josephson junction technologies for high speed digital applications , 1984 .

[57]  T. R. Gheewala,et al.  Design of 2.5-Micrometer Josephson Current Injection Logic (CIL) , 1980, IBM J. Res. Dev..

[58]  Y. Ichimiya,et al.  Josephson dual rail two-bit adder circuit utilizing magnetically coupled OR-AND gates , 1984, IEEE Transactions on Electron Devices.

[59]  S. Kotani,et al.  A 1ns Josephson 16b ALU , 1987, 1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[60]  M.B. Ketchen,et al.  A Josephson technology system level experiment , 1981, IEEE Electron Device Letters.

[61]  F. Yanagawa,et al.  A 4.2-ps logic gate using new Pb-alloy Josephson IC technology , 1985, IEEE Electron Device Letters.