Characterizing Processors for Time and Energy Optimization

Moore’s law [40] states that the number of transistors that can be most economically placed on an integrated circuit will double approximately every two years. The law has often been subjected to the following criticism: while it boldly states the blessing of technology scaling, it fails to expose its bane. A direct consequence of Moore’s law is that ”the power density of the integrated circuit increases exponentially with every technology generation” [45]. This implicit trend has arguably brought about some of the most important changes in electronic and computer designs. In the next two decades, diminishing transistor size, speed scaling and practical energy limit will create new challenges for continued performance scaling. As a result, the frequency of operations will increase slowly, with energy being the key limiter of performance, forcing designs to use large-scale parallelism, heterogeneous cores, and accelerators to achieve performance and energy efficiency. Energy and performance are important aspects of microprocessors and their verification and management require, measurement, estimation and analysis, and these aspects are discussed through this research. A processor executes a computing job in a certain number of clock cycles. The clock frequency determines the time that the job will take. Another parameter, cycle efficiency or cycles per joule, determines how much energy the job will consume. The execution time measures performance and, in combination with energy dissipation, influences power, thermal behavior, power supply noise and battery life. We describe a method for power management of a processor. To show management of performance and energy, we study several Intel processors from 45 nm, 32 nm and 22 nm technology nodes for both thermal design power (TDP) and peak power. They are characterized for two different predictive technology models: Bulk CMOS and High-K metal Gate, which are available for