论文信息 - Series resistance estimation and C(V) measurements on ultra thin oxide MOS capacitors

Series resistance estimation and C(V) measurements on ultra thin oxide MOS capacitors

Based on measurements on test structures with various electrical silicon oxide thicknesses (from 21 /spl Aring/ to 13 /spl Aring/) and areas (from 27000 /spl mu/m/sup 2/ to 2 /spl mu/m/sup 2/), this paper describes the effect of gate current on measured capacitance using a standard 10 kHz-to-1 MHz LCR-meter. We show that, in presence of high gate leakage, the series impedance, and also the channel debiasing, have a dramatic effect on observed C(V) curves. We also propose a segmented-MOS model, allowing discrete solution of the current continuity equation along the channel, which fits the measured C(V) and provides a solution for process monitoring (such as oxide thickness) and intrinsic capacitance determination for device modeling.

[1] N. Arora. MOSFET Models for VLSI Circuit Simulation , 1993 .

[2] Y. Tsividis. Operation and modeling of the MOS transistor , 1987 .

[3] K. Romanjek,et al. New approach for the gate current source–drain partition modeling in advanced MOSFETs , 2003 .

[4] R.S. Chau,et al. Inversion MOS capacitance extraction for high-leakage dielectrics using a transmission line equivalent circuit , 2000, IEEE Electron Device Letters.

[5] D.B.M. Klaassen,et al. Gate current: Modeling, /spl Delta/L extraction and impact on RF performance , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[6] Qi Xiang,et al. Impact of tunnel currents and channel resistance on the characterization of channel inversion layer charge and polysilicon-gate depletion of sub-20-/spl Aring/ gate oxide MOSFETs , 1999 .