A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layout sense amplifiers
暂无分享,去创建一个
Toshiaki Yamanaka | Katsuro Sasaki | Sadayuki Morita | Koichiro Ishibashi | F. Kojima | Atsuyoshi Koike | H. Iida | S. Ikeda | Kyoichiro Asayama | N. Hashimoto | K. Motohashi | Kunihiro Komiyaji | Toshiro Aoto
[1] K. Nakamura,et al. A 6-ns ECL 100 K I/O and 8-ns 3.3-V TTL I/O 4-Mb BiCMOS SRAM , 1992 .
[2] Noriyuki Suzuki,et al. A 6-ns 1-Mb CMOS SRAM with latched sense amplifier , 1993 .
[3] Hiroyuki Yamauchi,et al. A circuit design to suppress asymmetrical characteristics in high-density DRAM sense amplifiers , 1990 .
[4] H. Goto,et al. A 3.3-V 12-ns 16-Mb CMOS SRAM , 1992 .
[5] Noriyuki Suzuki,et al. A 150 ns 16-Mb CMOS SRAM with interdigitated bit-line architecture , 1992 .
[6] S. Hanamura,et al. A 9 ns 1 Mb CMOS SRAM , 1989, IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers.
[7] Evert Seevinck,et al. Current-mode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOS SRAM's , 1991 .
[8] K. Ishibashi,et al. A stacked split word-line (SSW) cell for low-voltage operation, large capacity, high speed SRAMs , 1993, Proceedings of IEEE International Electron Devices Meeting.
[9] Koichiro Ishibashi,et al. A 7-ns 140-mW 1-Mb CMOS SRAM with current sense amplifier , 1992 .