A 2-D semi-analytical model of parasitic capacitances for MOSFETs with high k gate dielectric in short channel

Abstract A 2-D semi-analytical model of parasitic capacitances for MOSFETs in ultra short channel, which takes the presence of high k gate dielectric into account, is developed. By using a semi-analytical method and an eigenfunction expansion method, we obtain part of expressions about capacitances. The model provides a good calculation method for parasitic capacitances and matches well with simulation results. It can be used in circuit simulation and device design directly.

[1]  S. De Gendt,et al.  Scaling of high-k dielectrics towards sub-1nm EOT , 2003, 2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672).

[2]  Anurag Mittal,et al.  Nano-CMOS Circuit and Physical Design , 2004 .

[3]  S. Narendra,et al.  Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors , 2003 .

[4]  Kunihiro Suzuki Parasitic capacitance of submicrometer MOSFET's , 1999 .

[5]  M.J. Kumar,et al.  On the parasitic gate capacitance of small-geometry MOSFETs , 2005, IEEE Transactions on Electron Devices.

[6]  P.T. Lai,et al.  Gate-leakage model of Ge MOS capacitor with high-k gate dielectric , 2006, 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings.

[7]  R. Shrivastava,et al.  A simple model for the overlap capacitance of a VLSI MOS device , 1982, IEEE Transactions on Electron Devices.

[8]  Jong-Ho Lee,et al.  A compact model of fringing field induced parasitic capacitance for deep sub-micrometer MOSFETs , 2009 .

[9]  Hyuck-In Kwon,et al.  A full analytical model of fringing-field-induced parasitic capacitance for nano-scaled MOSFETs , 2010 .