“ Accurate And Fast Power Estimation Of Large Combinational Circuits ”

A novel probabilistic method to estimate the switching activity of a logic circuit under a real delay gate model, is introduced. Based on Markov stochastic processes and generalizing the basic concepts of zero delay-based methods, a novel probabilistic model to estimate accurately the power consumption, is developed. More specifically, a set of new formulas, which describe first-order temporal correlation, under real delay model, are derived. The chosen gate model allows accurate estimation of the functional and spurious (glitches) transitions, leading to accurate power estimation. The proposed approach manipulates efficiently large circuits employing a new partitioning heuristic, which estimates the switching activity with reduced computational complexity. Comparative study and analysis of benchmark circuits demonstrates the accuracy and efficiency of the proposed method.