Priority-Based Routing Resource Assignment Considering Crosstalk
暂无分享,去创建一个
Yici Cai | Qiang Zhou | Bin Liu | Xianlong Hong | Yan Xiong
[1] Mattan Kamon,et al. FASTHENRY: a multipole-accelerated 3-D inductance extraction program , 1994 .
[2] Prashant Saxena,et al. On integrating power and signal routing for shield count minimization in congested regions , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[3] Sachin S. Sapatnekar,et al. A survey on multi-net global routing for integrated circuits , 2001, Integr..
[4] Jacob K. White,et al. FastCap: a multipole accelerated 3-D capacitance extraction program , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[5] Jiang Hu,et al. Congestion-driven codesign of power and signal networks , 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).
[6] Sudebkumar Prasant Pal,et al. A general graph theoretic framework for multi-layer channel routing , 1995, Proceedings of the 8th International Conference on VLSI Design.
[7] Jun Gu,et al. CNB: A critical-network-based timing optimization method for standard cell global routing , 2003, Journal of Computer Science and Technology.
[8] Rajendran Panda,et al. Early probabilistic noise estimation for capacitively coupled interconnects , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[9] Chandramouli V. Kashyap,et al. Block-based static timing analysis with uncertainty , 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).
[10] Rob A. Rutenbar,et al. Wire packing: a strong formulation of crosstalk-aware chip-level track/layer assignment with an efficient integer programming solution , 2000, ISPD '00.
[11] David Blaauw,et al. Inductance model and analysis methodology for high-speed on-chip interconnect , 2002, IEEE Trans. Very Large Scale Integr. Syst..
[12] Charles J. Alpert,et al. The ISPD98 circuit benchmark suite , 1998, ISPD '98.
[13] Weimin Shi,et al. Evaluation of closed-form crosstalk models of coupled transmission lines , 1999, ECTC 1999.
[14] Lei He,et al. Simultaneous shield insertion and net ordering under explicit RLC noise constraint , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[15] William Nicholls,et al. Track assignment: a desirable intermediate step between global routing and detailed routing , 2002, ICCAD 2002.
[16] Jinjun Xiong,et al. Full-chip routing optimization with RLC crosstalk budgeting , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[17] Yici Cai,et al. Layer assignment algorithm for RLC crosstalk minimization , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).
[18] Yao-Wen Chang,et al. Crosstalk-constrained performance optimization by using wire sizing and perturbation , 2000, Proceedings 2000 International Conference on Computer Design.
[19] C. L. Liu,et al. Minimum crosstalk channel routing , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[20] Min Zhao,et al. Layer assignment for crosstalk risk minimization , 2004 .
[21] George Papadopoulos,et al. Full-wave PEEC time-domain method for the modeling of on-chipinterconnects , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[22] Carl Sechen,et al. Timing- and crosstalk-driven area routing , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[23] Jun Chen,et al. Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization , 2004, ACM Trans. Design Autom. Electr. Syst..
[24] Yici Cai,et al. FaSa: A fast and stable quadratic placement algorithm , 2008, Journal of Computer Science and Technology.
[25] Yici Cai,et al. Crosstalk-Aware Routing Resource Assignment , 2005, Journal of Computer Science and Technology.