A carbon nanotube cortical neuron with spike-timing-dependent plasticity

This paper describes a carbon nanotube synapse circuit that exhibits Spike-Timing Dependant Plasticity (STDP). These synapses are found in cortical (e.g. pyramidal) neurons. Experiments with the synapse in a neuron circuit demonstrate changes in synaptic potential with pre- and post-spiking timing variations. The circuit design is biomimetic and changes in control voltages representing neurotransmitter concentration lead to changes in synaptic strength. The experiments are demonstrated with SPICE simulations using carbon nanotube transistor models.

[1]  Hicham Chaoui.  CMOS analogue adder , 1995 .

[2]  D. Johnston,et al.  Regulation of Synaptic Efficacy by Coincidence of Postsynaptic APs and EPSPs , 1997 .

[3]  P. Jonas,et al.  Kinetics of Mg2+ unblock of NMDA receptors: implications for spike‐timing dependent synaptic plasticity , 2004, The Journal of physiology.

[4]  Y. Dan,et al.  Spike Timing-Dependent Plasticity of Neural Circuits , 2004, Neuron.

[5]  Gordon M. Shepherd,et al.  Introduction to Synaptic Circuits , 2004 .

[6]  Kwabena Boahen,et al.  Learning in Silicon: Timing is Everything , 2005, NIPS.

[7]  Alan F. Murray,et al.  The Role of Membrane Threshold and Rate in STDP Silicon Neuron Circuit Simulation , 2005, ICANN.

[8]  Yu-Ming Chang,et al.  Increased action potential firing rates of layer 2/3 pyramidal cells in the prefrontal cortex are significantly related to cognitive performance in aged monkeys. , 2005, Cerebral cortex.

[9]  M. Prato,et al.  Biomedical applications of functionalised carbon nanotubes. , 2005, Chemical communications.

[10]  Aaron K. Friesz,et al.  A Biomimetic Carbon Nanotube Synapse Circuit , 2006 .

[11]  H. Wong,et al.  A Circuit-Compatible SPICE model for Enhancement Mode Carbon Nanotube Field Effect Transistors , 2006, 2006 International Conference on Simulation of Semiconductor Processes and Devices.

[12]  Chongwu Zhou,et al.  Novel nanotube-on-insulator (NOI) approach toward single-walled carbon nanotube devices. , 2006, Nano letters.

[13]  Alice C. Parker,et al.  Towards a Nanoscale Artificial Cortex , 2006, CDES.

[14]  Giacomo Indiveri,et al.  A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity , 2006, IEEE Transactions on Neural Networks.

[15]  Tetsuya Asai,et al.  Analog CMOS Circuits Implementing Neural Segmentation Model Based on Symmetric STDP Learning , 2007, ICONIP.

[16]  H. Wong,et al.  Impact of a Process Variation on Nanowire and Nanotube Device Performance , 2007, IEEE Transactions on Electron Devices.

[17]  Takashi Morie,et al.  A CMOS circuit for STDP with a symmetric time window , 2007 .

[18]  Chih-Chieh Hsu,et al.  A carbon nanotube implementation of temporal and spatial dendritic computations , 2008, 2008 51st Midwest Symposium on Circuits and Systems.

[19]  H.-S. Philip Wong,et al.  Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[20]  Alice C. Parker,et al.  A carbon nanotube cortical neuron with excitatory and inhibitory dendritic computations , 2009, 2009 IEEE/NIH Life Science Systems and Applications Workshop.