论文信息 - An On-Line BIST Technique for Delay Fault Detection in CMOS Circuits

An On-Line BIST Technique for Delay Fault Detection in CMOS Circuits

This paper presents a simulation-based study of the delay fault testing in CMOS logic circuits. A novel built-in self-test (BIST) technique is presented for detecting delay faults in this logic family. This scheme does not need test-pattern generation, and thus can be used for robust on-line testing. Simulation results for area, delay, and power overheads are presented.

S. Hessabi | E.K. Moghaddam

[1] Sudhakar M. Reddy,et al. Testable Realizations for FET Stuck-Open Faults in CMOS Combinational Logic Circuits , 1986, IEEE Transactions on Computers.

[2] Jacob Savir,et al. Random Pattern Testability of Delay Faults , 1988, IEEE Trans. Computers.

[3] Yashwant K. Malaiya,et al. Design of CMOS circuits for stuck-open fault testability , 1991 .

[4] K. Raahemifar,et al. Design-for-testability techniques for detecting delay faults in CMOS/BiCMOS logic families , 2000 .

[5] Michele Favalli,et al. Novel design for testability schemes for CMOS ICs , 1990 .

[6] Ali Keshavarzi,et al. DFT for delay fault testing of high-performance digital circuits , 2004, IEEE Design & Test of Computers.

[7] Shaahin Hessabi,et al. A design for-testability technique for shorts and bridging faults in BiCMOS logic families , 1995, Proceedings 1995 Canadian Conference on Electrical and Computer Engineering.

[8] Edward J. McCluskey,et al. Open faults in BiCMOS gates , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..