Reducing compilation time overhead in compiled simulators

Compiled simulation is a well known technique for improving the performance of instruction set simulators at the cost of compilation time. However the compilation time overhead makes such usage of compiler optimizations impractical especially for large applications. We propose a hybrid compiled simulation approach that is simple, generates an optimized decoder and has almost no compilation overhead comparing to static compiled simulation. Using two contemporary processor models- ARM7 and Sparc- we demonstrated that our technique can reduce the compilation time by 99% on the average, from several thousands of seconds to only tens of seconds.

[1]  Isabelle Sagnes,et al.  Proceedings 21st International Conference on Computer Design , 2000, Proceedings 21st International Conference on Computer Design.

[2]  David Keppel,et al.  Shade: a fast instruction-set simulator for execution profiling , 1994, SIGMETRICS.

[3]  Daniel D. Gajski,et al.  A retargetable, ultra-fast instruction set simulator , 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

[4]  Heinrich Meyr,et al.  Using static scheduling techniques for the retargeting of high speed, compiled simulators for embedded processors from an abstract machine description , 2001, International Symposium on System Synthesis (IEEE Cat. No.01EX526).

[5]  Nikil D. Dutt,et al.  Instruction set compiled simulation: a technique for fast and flexible instruction set simulation , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[6]  François Bodin,et al.  Mastering startup costs in assembler-based compiled instruction-set simulation , 2002, Proceedings Sixth Annual Workshop on Interaction between Compilers and Computer Architectures.