Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations

A new method for improving the timing yield offield-programmable gate array (FPGA) devices affected by intrinsicwithin-die variation is proposed. The timing variation is reducedby selecting an appropriate configuration for each chip from a setof independent configurations, the critical paths of which do notshare the same circuit resources on the FPGA. In this article, theactual method used to generate independent multiple configurationsby simply repeating the routing phase is shown, along with theresults of Monte Carlo simulation with 10,000 samples. Onesimulation result showed that the standard deviations of maximumcritical path delays are reduced by 28% and 49% for 10% and 30%Vth variations (σ/ μ), respectively,with 10 independent configurations. Therefore, the proposed methodis especially effective for larger Vth variation and isexpected to be useful for suppressing the performance variation ofFPGAs due to the future increase of parameter variation. Anothersimulation result showed that the effectiveness of the proposedtechnique was saturated at the use of 10 or more configurationsbecause of the degradation of the quality of the configurations.Therefore, the use of 10 or fewer configurations is reasonable.