Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations
暂无分享,去创建一个
Hanpei Koike | Toshiyuki Tsutsumi | Masakazu Hioki | Tadashi Nakagawa | Yohei Matsumoto | Takashi Kawanami | Toshihiro Sekigawa | T. Sekigawa | T. Nakagawa | H. Koike | M. Hioki | T. Tsutsumi | Y. Matsumoto | Takashi Kawanami
[1] Farid N. Najm,et al. An adaptive FPGA architecture with process variation compensation and reduced leakage , 2006, 2006 43rd ACM/IEEE Design Automation Conference.
[2] Jason Cong,et al. Optimality and Stability Study of Timing-Driven Placement Algorithms , 2003, ICCAD.
[3] K. Bowman,et al. Impact of extrinsic and intrinsic parameter fluctuations on CMOS circuit performance , 2000, IEEE Journal of Solid-State Circuits.
[4] James D. Meindl,et al. Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration , 2002, IEEE J. Solid State Circuits.
[5] Jonathan Rose,et al. Measuring the Gap Between FPGAs and ASICs , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[6] Narayanan Vijaykrishnan,et al. Variation aware placement for FPGAs , 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).
[7] Premachandran R. Menon,et al. Design-specific path delay testing in lookup-table-based FPGAs , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[8] Yan Lin,et al. FPGA device and architecture evaluation considering process variations , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..
[9] Vaughn Betz,et al. Architecture and CAD for Deep-Submicron FPGAS , 1999, The Springer International Series in Engineering and Computer Science.
[10] Hanpei Koike,et al. Performance and yield enhancement of FPGAs with within-die variation using multiple configurations , 2007, FPGA '07.
[11] John Wawrzynek,et al. Defect tolerance in multiple-FPGA systems , 2005, International Conference on Field Programmable Logic and Applications, 2005..
[12] Peter Y. K. Cheung,et al. Yield enhancements of design-specific FPGAs , 2006, FPGA '06.
[13] Andrzej Krasniewski. Evaluation of Testability of Path Delay Faults for User-Configured Programmable Devices , 2003, FPL.
[14] Andrew R. Brown,et al. Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs , 2003 .
[15] Vaughn Betz,et al. VPR: A new packing, placement and routing tool for FPGA research , 1997, FPL.
[16] Peter Y. K. Cheung,et al. Within-die delay variability in 90nm FPGAs and beyond , 2006, 2006 IEEE International Conference on Field Programmable Technology.
[17] Ning Lu,et al. Modeling FET Variation Within a Chip as a Function of Circuit Design and Layout Choices , 2005 .
[18] Jonathan Rose,et al. Measuring the Gap Between FPGAs and ASICs , 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[19] Costas J. Spanos,et al. Modeling within-field gate length spatial variation for process-design co-optimization , 2005, SPIE Advanced Lithography.
[20] Yan Lin,et al. Placement and Timing for FPGAs Considering Variations , 2006, 2006 International Conference on Field Programmable Logic and Applications.
[21] Xiao-Yu Li,et al. FPGA as Process Monitor-an effective method to characterize poly gate CD variation and its impact on product performance and yield , 2004, IEEE Transactions on Semiconductor Manufacturing.
[22] Jason Cong,et al. Optimality and Stability Study of Timing-Driven Placement Algorithms , 2003, ICCAD 2003.
[23] Jinjun Xiong,et al. FPGA Performance Optimization Via Chipwise Placement Considering Process Variations , 2006, 2006 International Conference on Field Programmable Logic and Applications.
[24] Kazutoshi Kobayashi,et al. A yield and speed enhancement scheme under within-die variations on 90nm LUT array , 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..
[25] Carl Ebeling,et al. PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs , 1995, Third International ACM Symposium on Field-Programmable Gate Arrays.