Dual Split-Merge: A high throughput router architecture for FPGAs

Abstract Modern FPGAs have become competitive platforms for System-on-Chip (SoC) designs resulting in the emergence of Network-on-Chip (NoC) paradigm as a promising solution for FPGAs interconnects problems. This paper proposes a high throughput FPGA-oriented router architecture denoted by Dual Split-Merge (DSM). The proposed architecture divides the router into two independent internal routers handling each network dimension. The division allows an incoming packet to face only half the complex logic and half the arbitration, increasing both the network throughput and the maximum operating frequency. Each internal router utilizes split and merge primitives that obviate the need for a switch crossbar and a switch allocater, decreasing the router area. The implementation results show the significant improvements in performance of the proposed router over the existing ones. The proposed router has a higher throughput than all other routers and a small network latency. A 4 × 4 network of DSM routers achieves a maximum throughput of 4.6 Gflits/s on Virtex-6 FPGA.